This invention relates to a demodulator for digital data which has been subjected to M.sup.2 (Modified Miller) modulation.
Various modulation formats have hithereto been proposed for transferring digital data in serial binary form to a recording medium such as a magnetic tape. One of such modulation formats is the M.sup.2 modulation format, which is described in detail in, for example, the specification of U.S. Pat. No. 4,027,335, and in which binary data are encoded in binary waveforms not including a component of direct current.
In an RZ (return-to-zero) format, which is another of the modulation formats for digital data in serial binary form, as is shown in FIG. 1(C), binary data are caused to correspond with the logical state (FIG. 1(B)) synchronously with clock pulses (FIG. 1(A)) and returned to a reference level between data bits. The NRZ - L (non-return-to-zero level) format and the NRZ - I (non-return-to-zero invert) format are improvements of the RZ format with the aim of heightening the recording density thereof. In the NRZ - L format, as is shown in FIG. 1(D), binary data are converted synchronously with a clock in correspondence with the logic state level of the binary data without returning to a reference level between data bits, and in the NRZ - I format, as is shown in Fig. (E), the polarity of binary data is inverted by causing it to transit synchronously with clock pulses only when the logical value of the binary data is 1.
Both NRZ formats, however, involve the risk of generation of a serious timing error because a signal maintains one or the other state for a comparatively long time. In addition, a transmission line for these formats requires a direct current transmission facility.
U.S. Pat. No. 3,108,261 discloses the Miller format in which the above-described defects are ameliorated. This format is, as is shown in FIG. 1(F), so constructed as to generate transition at an intermediate portion of each data bit of logical value 1 in binary data, and at the leading edge of each bit of logical value 0, except for a bit of logical value 0 which succeeds to a bit of logical value 1.
Though this Miller format requires a smaller bandwidth as compared with the NRZ formats, it does not exclude a component of direct current. Therefore if the transmission line has no direct current transmission facility, an error is generated.
A modification of the Miller format which enables the removal of the direct current component is the above-described format which is called M.sup.2 (Modified Miller) format. In this format, when an even number of data bits of the logical value 1 are in succession and an accumulated charge is not zero, transition is suppressed, as is shown in FIG. 1(G), thereby removing any component of direct current.
A demodulation system for decoding digital data which has been subjected to M.sup.2 modulation is also disclosed in U.S. Pat. No. 4,027,335. This demodulation system, however, in which NRZ - L type demodulated data is obtained by means of a multiplicity of direct conversion operations in relation to input data which has been subjected to M.sup.2 modulation (hereinunder referred to as M.sup.2 modulation data), requires a very complicated circuit structure.
Recently, a data separation circuit for separating M.sup.2 modulation data into data bits and clock bits by producing synchronizing clock pulses from M.sup.2 modulation input data, as is shown in FIG. 2, has been easily available as a single unit. However, no format for demodulating the M.sup.2 modulation data by utilizing the data separation circuit which produces such an output has yet been proposed.